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It obstructs the formation of silicon crystalline structure and completely decomposes the electrical and physical features of the wafer. The dislocations that are formed by slip can cause gate oxide integrity collapse, severe junction leakage, and untimely breakdown. The physical deformation can cause wafer breakage, pattern misalignment, chucking problems and focus instability.
A non-uniform temperature is produced in the silicon wafer during temperature furnace push. This causes a bright beaming energy from the kiln tube to heat up the wafer edge prior than the wafer center. This can also cause slip around the silicon wafer edge and the deformation of the silicon wafer. During temperature ramp-down and furnace pull, the wafer cools earlier at the edges than in the center.This cause temperature non-uniformity at the wafer center and causes the wafer to bend.
After years of experience in fabrication of ICs (on silicon wafers), engineers revealed that furnace slip has always created a problem. The engineers have always faced problems in increasing the speed of furnace, temperature ramps and push-pull to maximize the furnace output. However, at the same it is also necessary to restrain the speed of temperature ramps and push-pull to prevent wafer damage. Whenever a new IC technology produces extreme built-in device stress, the balance shifts. This is because furnace recipes which had earlier created slip-free silicon wafers became recipes which created massive furnace slip.
In the thermal cycling process, the stress which occurs on oxide is used on the trench of sidewalls. The thermal stress created due to temperature non-uniformities in the wafer generate slip dislocations and shift those dislocations into the leakage sensitive area of the device. Now days IC devices with STI structures can be fabricated easily by moderating both the furnace stress and the built-in IC device stress.
Temperature is the most important factor that controls the strength of the thermal oxide silicon wafers, and this must be kept in mind when setting temperature ramping and furnace pull/push conditions. The strength of the wafer decreases drastically when the temperature is increased from 700C to 800C. If wafers are pulled or pushed into a furnace with the tube set at 800C, the slip creates problem and can damage it. Therefore, the strength of the wafer is inversely proportional to the increase in temperature. It is essential to use lower ramping rates for higher temperature ranges to prevent wafer slip during furnace temperature ramping.
Other factors that affect the strength of the silicon wafer:
The higher the density of dislocations in a thermal oxide silicon wafer, the weaker the wafer. It takes a large stress to create a dislocation, but only a small stress can cause an existing dislocation to multiply or move.
The higher the interstitial oxygen concentration, the stronger the wafer. Dissolved or interstitial oxygen atoms connect themselves with dislocations and stop them from multiplying.
The higher the amount of precipitated oxygen, the weaker the wafer. Increasing oxygen precipitates use up the interstitial oxygen and blow out the new dislocations.
The higher the concentration of dopant atoms, the stronger the silicon wafers. The damaged fields around atoms, which are larger or smaller than the silicon atoms, obstruct the motion of dislocations.
Integrated circuit films can apply stress on the underlying silicon wafers and make slip more appropriate. Trench and other IC structures, as well as mechanical damage issues, can deteriorate the wafer by acting as stress concentrators.
